Virtual hardware-in-the-loop
Take the hardware
out of the loop.
Fly the firmware you ship against a simulated airframe on a laptop or a CI runner, and replay any run as it happened.
Free and open
The runtime that boots your firmware
Licensed per seat
The engine that closes the loop
A run, frame by frame
Watch the firmware's register traffic as it flies.
The quad takes off and catches a gust, and then one gyro axis freezes while the airframe keeps rolling. The access log fills in live, with sensor reads coming in and writes going out to the four motor timers and the telemetry port. Pause it to step through one access at a time.
live · 400 Hz · pause, or step one register access at a time
Hardware out of the loop
Both ends of the loop move into software.
The firmware runs on an emulated board and the airframe is a simulated plant. They share one clock, counted in instructions, so a run on a laptop and on a CI runner come out identical.
On a bench
In software
On a bench
The controller board
In software
An emulated MCU running your unmodified image
On a bench
The sensors and the ESCs on its buses
In software
Chip models answering on the same buses
On a bench
The airframe on a stand
In software
A plant stepped at 400 Hz
On a bench
Real time, which you can't pause or rewind
In software
A virtual clock that counts instructions
In your pipeline
Run your HIL tests in CI.
A merge request pipeline can do what the bench does. It boots the firmware, flies it against the plant, injects whatever faults the test asks for and checks the assertions, and nobody waits for a turn on the team's one HIL rig.
Results come back as JUnit, so GitLab shows them in the merge request with no extra setup. A failure reports the instruction it failed at, and rerunning it on a laptop stops at that instruction again.
A campaign the next morning looks something like this, one square per case, with the ones that broke the controller highlighted. Any of them replays the same way, since the only randomness in a run comes from its seed.
What it does
runtime
Boot the image you ship
It loads the ELF you'd flash to the board. You don't keep a second build with test hooks in it just for simulation.
runtime
Trace register accesses
Each access goes to a peripheral model written in Rust, and the trace prints it next to the instruction count where it happened.
runtime
Debug with GDB
When a breakpoint stops the core, the DMA engines, the timers and the plant stop with it. Step one instruction and everything else moves forward by that one instruction too.
engine
Inject faults in flight
Kill a sensor six seconds into a flight, or freeze one IMU while the other keeps reading true. The test case picks the moment and the run carries on without a restart.
engine
Replay any run
Sensor noise is drawn from the run's seed, so with the same inputs and seed, any machine that checks out the branch reproduces the run, x86 or Arm.
engine
A thousand runs overnight
Fly the same mission against a sweep of failures on the CI runners you already have, and come back in the morning to a short list of the cases that broke it.
Two commands
The CPU core ships inside the crate.
We wrote the core in Rust, and it's part of the rigless crate. It uses Cranelift to translate the firmware's instructions into host code and runs them on a separate thread in the same process, so there's no second binary to install and you don't need a C toolchain to build it.
The crate is MIT or Apache-2.0, whichever you prefer. Register tables generated from a vendor's SVD keep that vendor's license.
Free and paid
Open runtime · MIT or Apache-2.0
rigless
Boots an unmodified image on a supported MCU and serves GDB while it runs. It writes traces and runs your unit tests in CI. The bus, the SoC and board models, the SVD generator and the core all ship in one crate, and a board you model yourself gets the full rigless command from a small binary. Anyone can use it for free, commercially or not.
Engine · Rigless License
rigless-hil
Runs that firmware in instruction-counted lockstep with a simulated plant, injects faults and replays runs bit for bit. It's a commercial binary, but the plant interface is public in rigless-labs/hil, so you can see what your model has to implement before you ever talk to us. Prices are on the pricing page.
Have a controller to test?
Anyone can install the runtime today. If you want the engine, a plant model or a fault campaign, write and tell us which board you're on.